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  • Technical White Paper: Driving LVDS TFT LCD with STM32 MCU

    • Technical White Paper: Driving LVDS TFT LCD with STM32 MCU

    Introduction

    This blog outlines the steps required to interface an STM32F7 series MCU with Tianma TM121JDGP30 TFT LCD using the SN75LVDS83A LVDS transmitter. The STM32F7 MCU will drive the display via GPIO, DMA, and timers. The SN75LVDS83A converts the parallel RGB signals from the STM32F7 into LVDS signals, which are required by the TFT LCD.

    Key Challenges

    • Set up STM32F7 MCU's GPIO, timers and DMA to produce proper RGB data
    • LVDS signals must be generated correctly and transmitted to the LCD
    • Proper timing and synchronization are essential between the MCU, LVDS transmitter and the TFT display

    System Overview

    Key Components

    STM32F745 MCU

    • GPIO Pins: Used for transmitting RGB data (D0 to D23) and control signals (HSYNC, VSYNC, DE, PCLK).
    • Timers: Used to generate pixel clock (PCLK), HSYNC, VSYNC, and DE signals.
    • DMA: Used to efficiently transfer pixel data to GPIO pins.

    SN75LVDS83A LVDS Transmitter

    • Input: 24-bit RGB parallel data
    • Output: LVDS differential pairs
    • Clock: Differential clock input
    • Voltage: 3.3V logic

    TM121JDGP30 TFT LCD

    • Resolution: 1280x800 (WXGA)
    • Interface: 24-bit RGB input via LVDS
    • Voltage: 3.3V logic for control and data

    External Components: Level shifters (if necessary), resistors, capacitors, etc.

    STM32F745 MCU (GPIO & DMA) --> SN75LVDS83A LVDS Transmitter --> TM121JDGP30 TFT LCD

    LVDS Signal Requirements

    • The TM121JDGP30 TFT LCD uses 24-bit RGB888 input, and the SN75LVDS83A will convert these signals to LVDS.
    • The LCD requires synchronization signals like HSYNC, VSYNC, and DE to display content correctly.

    Steps to Interface STM32F745 with LVDS TFT LCD (TM121JDGP30)

    Step 1: Hardware Connection

    MCU to SN75LVDS83A

    • Connect the 24-bit RGB data lines (D0–D23) from STM32F745 GPIOs to the corresponding pins on the SN75LVDS83A.
    • Connect HSYNC, VSYNC, and DE signals from STM32F745 to the SN75LVDS83A for synchronization.
    • Connect PCLK from STM32F745 to the clock input on the SN75LVDS83A.

    SN75LVDS83A to TM121JDGP30

    • The SN75LVDS83A will convert the parallel RGB signals into LVDS signals. Connect the LVDS data pairs and clock to the appropriate pins on the TM121JDGP30.

    Step 2: GPIO Initialization

    • Configure STM32F745 GPIO pins for 24-bit RGB data and sync signals.
    • Set the pins for alternate function mode to handle the high-speed data transfer and synchronization.

    void GPIO_Init(void) {
        // Configure GPIO for RGB and sync signals (HSYNC, VSYNC, DE, PCLK)
        // Configure GPIO for 24-bit RGB and sync signals using STM32F745 GPIO library
    }

    Step 3: Timer Initialization

    • Set up timers to generate the pixel clock (PCLK), horizontal sync (HSYNC), vertical sync (VSYNC), and data enable (DE) signals.
    • Configure the timers with the required frequencies to match the TM121JDGP30 timing specification.

    void Timer_Init(void) {
       // Timer configuration to generate sync signals (HSYNC, VSYNC, DE) and pixel clock (PCLK)

    Step 4: DMA Setup

    • Use DMA to transfer pixel data from memory to the GPIO pins for efficient data transfer.
    • Configure the DMA in memory-to-peripheral mode to transfer RGB888 data.

    void DMA_Init(void) {
        // DMA configuration to efficiently transfer pixel data from memory to GPIO pins
    }

    Step 5: Sync Signal Generation

    To generate the sync signals (HSYNC, VSYNC, DE), the horizontal and vertical timing parameters from the TM121JDGP30 datasheet are used. These include timing for blanking periods and active display areas.

    void Sync_Generation(void) {
        // Horizontal sync signal generation logic (HSYNC)
        // Vertical sync signal generation logic (VSYNC)
        // Data enable signal generation logic (DE)
    }

    The detailed timing parameters from the datasheet are used to control when these signals are active. Here’s an example of how the sync signal generation is handled:

    • HSYNC is active during the horizontal blanking period and inactive during the active video area.
    • VSYNC is generated at the start of each frame.
    • DE is active during the pixel data transmission time (when both HSYNC and VSYNC are active).

    Step 6: Frame Buffer Management

    The frame buffer stores the pixel data (RGB888) and is periodically updated. The DMA transfers pixel data from the frame buffer to the GPIO pins connected to the LVDS transmitter.

    void loadImageData(uint8_t* imageData) {
        // Load RGB888 data into the frame buffer
    }
    void updateFrameBuffer(void) {
        // DMA transfer from frame buffer to GPIO
    }

    Step 7: Main Program

    In the main loop, the frame buffer is updated continuously, and sync signals are generated for each frame.

    int main(void) {
        HAL_Init();
        GPIO_Init();
        Timer_Init();
        DMA_Init();
        while (1) {
            updateFrameBuffer();   // Update the frame buffer periodically
            HAL_Delay(50);            // Adjust delay for desired frame rate (e.g., 60 Hz)
        }
    }

    Software Considerations

    Initialization Code

    • Initialize GPIO pins for RGB data and sync signals.
    • Set up timers to generate the required sync signals and pixel clock.
    • Configure DMA to transfer pixel data from memory to GPIO pins.

    Pixel Data Formatting

    • Pixel data is in RGB888 format, so no conversion is needed.
    • Each pixel is represented by 24 bits: 8 bits for Red, 8 bits for Green, and 8 bits for Blue.

    Display Update

    • Periodically update the display by sending new data frames to the LVDS transmitter via DMA.

    Sync Signal Timing

    The TM121JDGP30 timing specification defines the following parameters for generating sync signals:

    • Horizontal Total Period (tH): The total time for one horizontal line.
    • Horizontal Back Porch (tHBP): The blanking period before the active display area.
    • Horizontal Front Porch (tHFP): The blanking period after the active display area.
    • Vertical Total Period (tV): The total time for one frame.
    • Vertical Back Porch (tVBP) and Vertical Front Porch (tVFP) are similar to their horizontal counterparts but for the vertical axis.

    These timing parameters dictate when to start and stop generating HSYNC, VSYNC, and DE signals.

    Conclusion

    The STM32F745 MCU can successfully drive the TM121JDGP30 TFT LCD via the SN75LVDS83A LVDS transmitter. By configuring GPIO, timers, and DMA, the MCU can generate the required synchronization signals and pixel data, transmitting them to the LVDS transmitter, which then drives the LCD. This approach provides flexibility and control over the display, even without a dedicated LCD controller.

    References

    • STM32F745 Reference Manual
    • SN75LVDS83A Datasheet
    • TM121JDGP30TFT LCD Datasheet
    • LVDS Signal Standards
    • STM32 HAL Library Documentation
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